The present invention relates to a low-consumption power-on reset circuit for semiconductor memories.
As is known, in semiconductor memories, it is essential for the supply voltage to be kept stable, and in any event higher than a predetermined threshold. In fact, otherwise, errors may occur during reading and writing, and, in addition, data contained in configuration registers may be adversely affected. For this reason, semiconductor memories are normally provided with power-on reset circuits, which, if the supply voltage drops excessively, generate a power-on reset pulse (called hereinafter POR pulse), in order to inhibit the operations of reading and writing, and to re-initialize the configuration registers.
For greater clarity, reference is made to FIGS. 1 and 2, showing two examples of power-on reset circuits of a known type.
In FIG. 1, the reference number 1 indicates a power-on reset circuit of a semiconductor memory device 100, comprising a first divider 2, an inverter 3, and an output terminal 9.
The first divider 2 is connected between ground and a supply line 5 supplying a supply voltage VDD, of, for example, 6 V, and includes a first resistive branch 6 and a variable resistive network 7. The first resistive branch 6 comprises a transistor of NMOS type in diode configuration, with drain and gate terminals connected to one another. The first resistive branch 6 and the variable resistive network 7 are connected at an intermediate node 8, supplying a first division voltage VPR proportional to the supply voltage VDD, according to the division ratio of the divider 2. The variable resistive network 7 comprises a second resistive branch 7a, formed by a plurality of resistive transistors 4 arranged in series and having respective gate terminals connected to the supply line 5, and by a connectable transistor 7b of NMOS type, arranged in parallel with the second resistive branch 7a and having a gate terminal connected to the output terminal 9.
The inverter 3, normally of CMOS type having trip voltage, receives at the input the first division voltage VPR, has an output connected to the output terminal 9, and supplies a reset signal POR.
In normal functioning conditions, i.e., when the supply voltage VDD is higher than a first threshold, the first division voltage VPR is higher than the trip voltage of the inverter 3, and thus the reset signal POR is set to a low logic level, such that memory reading and writing are enabled. In addition, the connectable transistor 7b is off.
During transitory, e.g., when the memory device is switched on, or in presence of noise, if the supply voltage VDD is below a first threshold, the first division voltage VPR is lower than the trip voltage of the inverter 3. Consequently, the reset signal POR switches to a high logic level, thus inhibiting reading and writing of the memory, and reinitialization of the configuration registers. In addition, the connectable transistor 7a is on, and thus the resistance value of the variable resistive network 7 is varied, together with the division ratio of the divider 2, and consequently the value of the first division voltage VPR.
As the supply voltage VDD increases, and exceeds a second threshold, greater than the first threshold, and causes further switching of the inverter 3, the reset signal POR goes to the low logic level, and reading and writing are enabled once more.
According to a different solution, shown in FIG. 2, the power-on reset circuit 1 comprises an enabling stage 11, formed by the same components of the power-on reset circuit 1 of FIG. 1 (and therefore indicated by the same reference numbers), and a generation stage 12.
The generation stage 12 comprises a second divider 15 and a comparator 18. The second divider 15 has a first terminal connected to ground and a second terminal connected to the supply line 5, via a switch 16. The comparator 18 has a first input connected to a second intermediate node 19 of the second divider 15, a second input which receives a constant reference voltage VREF, and an output, which defines an output terminal 20 of the power-on reset circuit 1, and supplies the reset signal POR. In addition, the switch 16 has a control terminal connected to the output terminal 9 of the enabling stage 11, which selectively enables and deactivates the generation stage 12, and thus the switching of the reset signal POR. In particular, when the signal at the output terminal 9 of the enabling stage 11 is at the low logic level (i.e., the supply voltage VDD is higher than the first threshold, and close to the nominal value), the switch 16 is open and the generation stage 12 is deactivated. In particular, in this phase, the reset signal POR is at the low logic level, such as to allow reading and writing. If, on the other hand, the supply voltage VDD drops below the first threshold, the signal at the output terminal 9 of the enabling stage 11 causes the switch 16 to close, thus enabling the generation stage 12. In this situation, the reset signal POR is at the low logic level, if the voltage at the second intermediate node 19 (which is proportional to the supply voltage VDD according to the ratio of division of the second divider 15) is greater than the reference voltage VREF, otherwise it is at the high logic level, such as to inhibit reading and writing, and to re-initialize the registers.
The known devices have some disadvantages, mainly due to the operating conditions of the inverter 3 and of the first divider 2. In fact, during normal functioning, i.e., when the supply voltage VDD is close to its nominal value, the division voltage VPR at the first intermediate node 8 is at a lower value than the supply voltage VDD, according to the ratio of division between the first resistive branch 6 and the variable resistive network 7. Consequently, the inverter 3 is conducting, and thus power is absorbed even when the inverter 3 does not switch, thus increasing the consumption of the memory device 100. In addition, the conductivity of the divider 2, and consequently the absorbed current, depend on the value of the supply voltage VDD, and are maximal in nominal functioning conditions.
The object of the present invention is to provide a power-on reset circuit which is free from the disadvantages described, and in particular has reduced consumption.
According to the present invention, a power-on circuit for semiconductor memories is provided, the circuit including a supply line set to a supply voltage; an output terminal supplying a reset logic signal; a divider connected between the supply line and a reference power line and having an intermediate node that supplies a division voltage correlated to the supply voltage and connected to the output terminal; and deactivation circuitry coupled to the supply line and the intermediate node, the deactivation circuitry being active and preventing switching of the reset logic signal when the supply voltage is higher than a deactivation voltage. Ideally, the deactivation circuit is inactive when the supply voltage is lower than the deactivation voltage.
In accordance with another aspect of the present invention, a power-on reset circuit is provided that includes a supply line set to a supply voltage; a supply circuit coupled to the supply line and configured to generate a division voltage at an intermediate node; an inverter connected between the intermediate node and an output terminal and configured to output a power-on reset signal when the supply voltage is less than a threshold value; and a deactivation circuit coupled to the supply line and the intermediate node, the deactivation circuit configured to prevent output of the power-on reset signal to maintain the division voltage at a voltage that is approximately the value of the supply voltage such that the inverter does not absorb current when the supply voltage is above the threshold value. Ideally, the supply circuit is configured to absorb little current when the supply voltage is above the threshold value.
In accordance with a further aspect of the present invention, a power-on reset circuit is disclosed that includes a voltage divider circuit coupled between a ground potential and a supply line that supplies a supply voltage, the voltage divider circuit configured to output a division voltage at an intermediate node;
an inverter coupled between the intermediate node and an output terminal and configured to output a power-on reset signal when the supply voltage is below a first threshold value; and a deactivation circuit coupled to the supply line and to the intermediate node, the deactivation circuit configured to prevent output of the power-on reset signal and to maintain the division voltage at approximately the supply voltage level when the supply voltage is above a second threshold voltage.